1. Field of the Invention
This invention relates to a semiconductor memory device, in which electrically rewritable and non-volatile memory cells are arranged.
2. Description of Related Art
A NAND-type flash memory is known as one of EEPROMs, which is constituted by arranging electrically rewritable and non-volatile semiconductor memory cells. In the NAND-type flash memory, a plurality of memory cells are connected in series in such a manner that adjacent two cells share a source/drain diffusion layer, thereby constituting a NAND cell unit. The NAND-type flash memory has a basic property that the unit cell area is smaller than that of NOR-type one, thereby being possible to easily achieve a great memory capacitance.
A sense amplifier circuit of the NAND-type flash memory is usually formed to have a clamping transistor for clamping the bit line voltage and transferring a bit line voltage to a sense node, a precharging transistor for precharging a bit line and the sense node and a data latch for storing the bit line data transferred to the sense node.
If the bit line pitch is more miniaturized, it becomes difficult to dispose sense amplifiers at the respective bit lines, and influence of noises between adjacent bit lines will be increased. For this reason, a shared sense amplifier scheme is usually utilized, in which adjacent two bit lines share a sense amplifier. In this scheme, a non-selected bit line disposed adjacent to a selected bit line is used as a shield line at a data read time. Further, in this shared sense amplifier scheme, it is prepared a bit line select circuit in a sense amplifier circuit, and a sense amplifier is selectively coupled to one of the adjacent two bit lines (see, for example, Unexamined Japanese Patent Application Publication No. 2003-249083).
In the NAND-type flash memory, data erasure is performed by a block. At a data erase time, an erase voltage of about 20V is applied to a p-type well on which the memory cell array is formed under the condition of: the entire word lines in a selected block are set at 0V; and the entire bit lines are set in a floating state. At this time, the bit lines will be boosted to about 20V because a forward bias is applied between the n-type diffusion layer to which the bit lines are connected and the p-type well.
In consideration of the above-described bit line boost at the data erase time, it is required to use a high voltage transistor as a bit line select transistor (i.e., a gate insulating film of which is thicker than that of a clamping transistor) in the sense amplifier.
On the other hand, the connect node SABL is usually formed as a signal wiring running in parallel with the bit lines due to the layout convenience of the sense amplifier circuit. With this layout, if the bit lines are boosted in voltage at the data erase time, the connect node SABL disposed adjacent to the bit lines will be boosted by capacitive coupling. Therefore, there is danger that the clamping transistor, i.e., a low voltage transistor, may be destroyed.